1. Thisposition is for a digital/ASIC design engineer to build next-generationanalog/digital mixed SoC chips.
2. Handlingevery aspect in ASIC design flow including architecture, RTL coding,Verification, Synthesis, DFT, STA and P&R.
3. Participateinto the chip debug and validation.
1. BSEEwith minimum 3-year of working experience or MSEE with minimum 1-year ofworking experience for starting position
2. MSEEwith minimum 3-year of working experience for senior position.
3. Excellentknowledge for ASIC design, such as MOS transistor, arithmetic structure(addition, multiplication), timing analysis, design for test, meta-stabilityand etc.
4. Needfundamental understanding for digital signal processing, such as FIR/IIR filterstructure, digital error correction, decimation/interpolation and etc.
5. Usageexperience (not all of them required) of industry-standard EDA tools, such asVCS/NC, Design Compiler, Primetime, Formality/Conformal and Tetramer/DFTcompiler.
6. Experiencein bus design (SPI, I2C, AHB or AIX), data path design (Filter, correlation orCodec), SerDescontroller (PCS and MAC) and PHY (channel encoder/decoder) willbe a plus.
7. Experiencein metrics driven verification methodology (system Verilog/UVM based) will be aplus.
8. Experiencein every aspect of ASIC design will be a great plus.